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features ? secure battery authentication ? superior sha - 256 hash algorithm ? best in class 256 - bit key length ? guaranteed unique 48-bit serial number ? high speed single wire interface ? supply voltage : 2. 7 ? 5. 2 5v ? <100na sleep current ? 4kv esd protection ? green comp liant (exceeds rohs) 3 - pin sot - 23 package and 8 - lead tssop or soic applications ? cell phones ? pda and smart phones ? portable media players ? digital cameras & camcorders ? cordless tools ? handheld devices 1. introduction the atmel ? at88 sa100s is a small authenticatio n chip that can be used to validate battery packs and other replaceable items that contain a power source. it uses the industry leading sha - 256 hash algorithm to provide the ultimate level of security. an ind ustry leading key length of 256 - bits prevents ex haustive attacks while multiple physical security features prevent unauthorized disclosure of the secret key stored within the chip . this key is automatically erased when power is removed from the at88sa100s . it is ship ped with a guaranteed unique 48 - bit s erial number that is used in combination with an input challenge and the stored secret key to generate a response that is unique for every individual at88sa100s . the chip also includes 8 0 one - time fuses that can be used to configure the system and/or retai n permanent status. the values in these fuses can also be locked to prevent modification. atmel cryptoauthentication atmel at88sa100s battery authentication chip 8558e ? smem ? 8/10
2 atmel a t88sa10 0 s 8558e ? smem ? 8/10 1.1. memory resources sram 256- bits of sram are used for storage of a key. the loadsram command provides a mechanism to securely initialize this block during personal ization . this memory will retain its value when the chip is put/goes to sleep, so long as a supply voltage in excess of v retain is still supplied to the chip. memvalid a single bit that tells whether or not sram contains valid data. it?s cleared when power is lost and set when the sram is loaded with a secret key. fuse block of 128 - fuse bits that can be read and written through the one wire interface. the first 8 - bits are lock bits that control burn ability on 16 - bit words of the array. fuse[88 - 95] are par t of the manufacturing id values fixed by atmel ? . fuse[96 - 127] are part of the serial number programmed by atmel which is guaranteed to be unique. see section 1.3 for more details on the manufacturing id and ser ial number. rom metal mask programmed memory. unrestricted read s are permitted on the first 64 - bits of this array. the physical rom will be larger and will contain other information that cannot be read. rom mfr id two bytes of rom that specifies part of th e manufacturing id code. this value is assigned by atmel and is always the same for all chips of a particular model number. for the atmel at88sa100s, this value is 0x 23 01 . (appears on the bus: 0x01 23) rom mfrid can be read by accessing rom bytes 0 & 1 of address 0. rom sn two bytes of rom that can be used to identify chips among others on the wafer. these bits reduce the number of fuses necessary to construct a unique serial number. the rom sn is read by accessing rom bytes two and three of address 0. th e serial number can always be read by the system and is optionally included in the message digested by the mac command. revnum four bytes of rom that are used by atmel to identify the design revision of the at88sa100s chip. these bytes can be freely read a s the four bytes returned from rom address 1, however system code should not depend on this value as it may change from time to time. 1.2. fuse map the at88 sa100s chip incorporates 128 one - time fuses within the chip. once burned, there is no way to reset the va lue of a fuse. fuses, with the exception of the manufacturing id and serial number bits , which are initialized by atmel, have a value of one when shipped from the atmel factory and transition to a zero when they are burned. table 1 -1. the 128 fuses in the atmel at88 sa100s chip are arranged in the following manner: fuse # name description 0 ? 7 fuse lock bits each bit , when zero , locks the current value of the corres ponding 16 - bit block of the fuse array, see below for more details 8 ? 87 status fuses these fuses ca n be written with the burn fuse command and can always be read with the read command 88 ? 95 fuse mfrid see section 1.3 . set by atmel, can?t be modified in the field 96 ? 127 fuse sn see section 1.3 . set by atmel, can?t be modified in the field
atmel at88sa10 0 s 3 8558e ? smem ? 8/10 fuse lock bits these eight fuses can be used to prevent further writing of the status fuses. bit zero , when burned, locks fuse[0 - 15] from being modified, bit[1] locks fuse[16 - 31] and so on up through bit five , which locks fuse[80 - 87]. fuse[88 - 127] can never be modified with the burnfuse command. note: b urning bit zero has the effect of preventing any changes to the current value of the lock bits status fuses these fuses can be used to store various information which are not secret . t heir value can always be determined using the read command. they can be individually burned using the burnfuse command. two common usage models for these fuses are : 1. consumption logging, i.e. burn one bit after every n uses, the host system keeps track of the number of uses so far for this serial number since the last fuse burn . 2. model number information. in this situation, the bits are written at the factory and their value is locked to prevent mo difications in the field. this method can also be used for feature enabling. 1.3. chip identification the chip includes a total of 72 - bits of information that can be used to distinguish between individual chips in a reliable manner. the information is distribut ed between the rom and fuse blocks in the following manner. serial number this 48 - bit v alue is composed of rom sn (16 - bits) and fuse sn (32 - bits). together they form a serial number that is guaranteed to be unique for all devices ever manufactured within t he atmel ? cryptoauthentication ? family. this value is optionally included in the mac calculation. manufacturing id this 24 - bit val ue is composed of rom mfrid (16 - bits) and fuse mfrid (8 - bits). typically this value is the same for all chips of a given type . it is always included in the cryptographic computations.
4 atmel a t88sa10 0 s 8558e ? smem ? 8/10 1.4. sha - 256 computation this chip perform s only one cryptographic calculation ? a key ed digest of an input challenge using the sha - 256 algorithm, d ocumented here: http://csrc.nist.gov/publications/fips/fips180 - 2/fips180 - 2.pdf 1.4.1. sha computation example in order to ensure that there is no ambiguity, the following example vector is provided in addition to the sample vectors in the nist document. in this example, all values are listed in hex. for all but the key, bytes are listed in the order that they appear on the bus ? first on the left. key is listed in the same order, so the 01 at the left of the key string is th e first byte passed to sha - 256. key 01030507090b0d0f11131517191b1d1f21232527292b2d2f31333537393b3d3f challenge 020406080a0c0e10121416181a1c1e20222426282a2c2e30323436383a3c3e40 opcode 0 8 mode 40 (include serial number in message) param2 0000 fuse mfrid 77 fuse s/n 8899aabb rom mfrid ccdd rom sn eeff the 88 - bytes over which the digest is calculated are : 0103?3d3f0204?3e4001400000?eeff digest : 7d38245733717a488575b9f794f7bcafe033a3848d39430da25141fdebeaa1c2 a read command executed on address zero of the rom ( rom mfrid , rom sn ) would return cc dd ee ff, with cc being the first byte on the bus and ff being the last. throughout this document, the compl ete message processed by the sa1 00s chip is documented. according to the above specification, this alw ays includes a single bit of ?1? pad afte r the message, followed by a 64 - bit value representing the total number of bits being hashed (less pad and length). if the length is less than 447 (512 - 64 - 1) then the necessary number of ?0? bits are included betwee n the ?1? pad and ?length? to stretch th e last message block out to 512 - bits. when using standard libraries to calculate the sha - 256 digest, these pad and length bits should probably not be passed to the library as most standard software implementations of the algorithm add them in automatically.
atmel at88sa10 0 s 5 8558e ? smem ? 8/10 1.5. security features th e atmel ? at88sa100s incorporates a number of physical security features designed to protect the key from unauthorized release. these include an active shield over the entire surface of the int ernal memory encryption, internal clock generation, glitch protection, voltage tamper detection and other physical design features. both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two sig nals. 2. io protocol communications to and from th e at88sa100s take place over a single asynchronously timed wire using a pulse count scheme . the overall communications structure is a hierarchy: table 2 -1. io hierarchy tokens implement a single data bit transmitted o n t he bus, or the wake - up event flags comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (i f any) which may be transmitted blocks o f data follow the command and t ransmit flags. they incorporate both a byte coun t and a checksum to ensure proper data transmission packets o f bytes form the core of the block without the count and crc. they are either the input or output parameters of a n atmel at88 sa100s chip command or status information from the atmel at88 sa100s c hip 2.1. io tokens there are a number of io tokens input: (to at88sa100s ) that may be transmitted along the bus: wake wake at88sa100s up from sleep (low power) state zero send a single bit from system to the at88sa100s with a value of zero one send a single bi t from system to the at88sa100s with a value of one output: (from at88sa100s ) zeroout send a single bit from the at88sa100s to the system with a value of zero oneout send a single bit from the at88sa100s to the system with a value of one the waveforms are the same in either direction, however there are some differences in timing based on the expectation that the host has a very accurate and consistent clock while the at88sa100s has significant variation in its internal clock generator due to normal manufact uring and environmental fluctuations . the bit timings are designed to permit a standard uart running at 230.4k baud to transmit and receive the tokens efficiently. each byte transmitted or received by the uart corresponds to a single bit received or transm itted by the at88sa100s . refer to applications notes on atmel?s website for more details describing how the uart should be controlled.
6 atmel a t88sa10 0 s 8558e ? smem ? 8/10 2.2. ac parameters figure 2 -1. ac parameters t start t zhi t zlo data comm wake logic ? t start t bit logic 1 t lignore t hignore noise suppresion t wlo t whi 3. absolute maximum ratings * operating temperature ............... ? 40c to +85c storage temperature ............... ? 65c to + 150c voltage on any pin with respect to ground ........... ? 0.5 to v cc +0.5v * notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device r eliability.
atmel at88sa10 0 s 7 8558e ? smem ? 8/10 table 3 -1. ac parameters parameter symbol direction min typ max unit notes wake low duration t wlo to atmel cryptoauthentication 60 - s signal can be stable in either high or low levels during extended sleep intervals. wake delay to data comm. t whi to atmel cryptoauthentication 2.5 45 ms signal should be stable high for this entire duration. t whi must not exceed t timeout or the chip will transition to sleep. start pulse duration t start to atmel cryptoauthentication 4.1 4.34 4.5 6 s from cryptoauthentication 4.6 6.0 8.6 s zero transmission high pulse t zhi to atmel cryptoauthentication 4.1 4.34 4.5 6 s from atmel cryptoauthentication 4.6 6.0 8.6 s zero transmission low pulse t zlo to atmel cryptoauthentication 4.1 4.34 4.5 6 s from atmel cryptoauthentication 4.6 6.0 8.6 s bit time (1) t bit to atmel cryptoauthentication 37 39 - s if the bit time exceeds t timeout then the atmel cryptoauthentication will enter sleep mode and the w ake token must be resent. from atmel cryp toauthentication 4 1 54 7 8 s turn around delay t turnaround from atmel cryptoauthentication 2 8 60 95 s atmel cryptoauthentication will initiate the first low going transition after this time interval following the end of the transmit flag to atmel cr yptoauthentication 15 s 4 6 m s after atmel cryptoauthentication transmits the last bit of a block, system must wait this interval before sending the first bit of a flag high side glitch filter @ active t hignore_a to atmel cryptoauthentication 45 ns pul ses shorter than this in width will be ignored by the chip, regardless of its state when active low side glitch filter @ active t lignore_a to atmel cryptoauthentication 45 ns pulses shorter than this in width will be ignored by the chip, regardless of its state when active low side glitch filter @ sleep t lignore_s to atmel cryptoauthentication 2 s pulses shorter than this in width will be ignored by the chip when in sleep mode io timeout t timeout to atmel cryptoauthentication 45 65 85 ms refer to section 4.4.1 watchdog reset t watchdog to atmel cryptoauthentication 3 4 5. 7 s max. time from w ake until chip is forced into s leep mode see watchdog failsafe , section 4.5
8 atmel a t88sa10 0 s 8558e ? smem ? 8/10 4. dc parameters table 4 -1. dc parameters parameter symbol min typ max unit notes operating temperature t a -40 85 c power supply voltage v cc 2. 7 5. 2 5 v fuse burning voltage v burn 3. 0 5 . 2 5 v voltage is applied to v cc pin during burnsecure and/or burnfuse active power supply current i cc - 6 ma sleep power supply current @ - 40 to 55c i sleep 100 na when chip is in sleep mode, v cc = 5.25 v, vsig = 0.0 to 0.5 v or vsig = v cc - 0.5v to v cc . sleep power supply current @ 85c i sleep 1 a when chip is in sleep mode, v cc = 5.25v, vsig = 0.0 to 0.5v or vsig = v cc - 0.5v to v cc . input low voltage @ v cc = 5. 2 5v v il - 0.5 . 1 5 * v cc v voltage levels for w ake token when chip is in sleep mode inp ut low voltage @ v cc = 2. 7 v v il - 0.5 0.5 v voltage levels for w ake token when chip is in sleep mode input high voltage @ v cc = 5. 2 5v v ih .25 * v cc 5.25 v voltage levels for w ake token when chip is in sleep mode input high voltage @ v cc = 2. 7 v v ih 1. 0 3.0 v voltage levels for w ake token when chip is in sleep mode input low voltage when active v il - 0.5 0. 5 v when chip is in active mode, v cc = 2. 7 ? 5. 2 5v input high voltage when active v ih 1.2 5.25 v when chip is in active mode, v cc = 2. 7 ? 5. 2 5v output low voltage v ol 0.4 v when chip is in active mode, v cc = 2. 7 ? 5. 2 5v maximum input voltage v max 5.25 v esd v esd 4 kv human body model, sig & v cc pins
atmel at88sa10 0 s 9 8558e ? smem ? 8/10 4.1. io flags the host system is always the bus master, so before any io transactio n, the system must first send an 8 - bit flag value to the chip to indicate the io operation that is to be performed, as follows: name meaning 0x77 command after this flag, the system starts sending a command block to the chip. the first bit of the block ca n follow immediately after the last bit of the flag. 0x88 transmit after a turn - around delay, the chip will start transmitting the response for a previously transmitted command block. 0xcc sleep upon receipt of a sleep flag, the chip will enter a low pow er mode until the next w ake token is received. all other values are reserved and will be ignored. 4.1.1. command timing after a command flag is transmitted, a command block should be sent to the chip. during parsing of the parameters and subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin. the delays for these operations are listed in the table below: table 4 -2. command timing parameter symbol max unit notes parsingdelay t parse 100 s delay to check crc and parse opcode and parameters before an error indication will be available memorydelay t exec_mem 3 m s delay to execute read, write and/or sramlock commands fusedelay t exec_fuse 700 s delay to execute burnfuse command at v cc > 4.5v s ee section 5.3 for more details macdelay t exec_mac 30 ms delay to execute mac command personalizedelay t person 13 ms delay to execute genpersonalizationkey or loadsram in this document, t exec is used as shorthand for the delay corresponding to whatever command has been sent to the chip.
10 atmel a t88sa10 0 s 8558e ? smem ? 8/10 4.1.2. transmit flag the t ransmit flag is used to turn around the signal so that the atmel ? at88sa100s can send data back to the system, depending on its current state. the bytes tha t the at88sa100s returns to the system, depending on its current state as follows: table 4 -3. return codes state description error/status description after w ake, but prior to first command 0x11 indication that a proper w ake token has been received by the atmel at88s a100s after successful command execution ? return bytes per ?output parameters? in command section of this document. in some cases this is a single byte with a value of 0x00 indicating success. the t ransmit flag can be resent to the atmel at88sa100s repea tedly if a re - read of the output is necessary. execution error 0x0f command was properly received but could not be executed by the atmel at88 sa100s chip . changes in the atmel at88 sa100s chip state or the value of the command bits must happen before it is re - attempted. after crc or other parsing error 0xff command was not properly received by atmel at88sa100s and should be re - issued by the system. the at88sa100s always transmits complete blocks to the system, so in the above table the status/error bytes result in 4 - bytes going to the system ? count, error, crc x 2. after receipt of a command block, the at88sa100s will parse the command for errors, a process which takes t parse ( refer to 4.1.1 ). after this inter val the system can send a t ransmit token to the at88sa100s ? if there was an error then the at88sa100s will respond with an error code. if there is no error then the at88sa100s internally transitions automatically from t parse to t exec and will not respond to any t ransmit tokens until both delays are complete. 4.1.3. sleep flag the sleep flag is used to transition the at88sa100s to the low power state, which causes a complete reset of the at88sa100s ? internal command engine and input/output buffer. it can be sent t o the at88sa100s at any time when the at88sa100s will accept a flag. to achieve the specified i sleep atmel recommends that the input signal be brought below v il when the chip is asleep. to achieve i sleep if the sleep state of the input pin is high, the vol tage on the input signal should be within 0.5v of v cc to avoid additional leakage on the input circuit of the chip. 4.1.4. pause state the pause state is entered via the pauselong command and can be exited only when the watchdog timer has expired and the chip tra nsitions to a sleep state. when in the pause state, the chip ignores all transitions on the signal pin but does not enter a low power consumption mode. the pause state provides a mechanism for multiple at88 sa10 0 s chips on the same wire to be selected and t o exchange data with the host microprocessor. the pauselong command includes an optional address field which is compared to the values in fuses 84 - 87. if the two match, then the chip enters the pause state, otherwise it continues to monitor the bus for sub sequent commands. the host would selectively put all but one at88 sa10 0 s in the pause state before executing the mac command on the active chip. after the end of the watchdog interval all the chips will have entered the sleep state and the selection process can be started with a w ake token (which will then be honored by all chips) and selection of a subsequent chip.
atmel at88sa10 0 s 11 8558e ? smem ? 8/10 4.2. io blocks commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way: byte nu mber name meaning 0 count number of bytes to be transferred to the chip in the block, including count, packet and checksum, so this byte should always have a value of (n+1). the maximum size block is 39 and the minimum size block is four . values outside t his range will cause unpredictable operation. 1 to (n -2) packet command, param eters and data, or response see section 5 for more details n - 1, n checksum crc- 16 verification of the count and pack et bytes . the crc polynomial is 0x8005, the initial register value should be zero and after the last bit of the count and packet have been transmitted the internal crc register should have a value that matches that in the block. the first byte transmitted (n - 1) is the least significant byte of the crc value so the last byte of the block is the most significant byte of the crc. 4.3. io flow the general io flow for a mac command is as follows: 1. system sends w ake token 2. system sends transmit flag 3. receive 0x11 value from the atmel at88sa100s to verify proper wakeup synchronization 4. system sends command flag 5. system sends command block 6. system waits t parse for the atmel at88sa100s to check for command formation errors 7. system sends transmit flag. if command format is ok, t he atmel at88sa100s ignores this flag because the computation engine is busy. if there was an error, the atmel at88sa100s responds with an error code 8. system waits t exec . refer to 4.1.1 9. system sends transmit flag 10. receive output block from the atmel at88sa100s , system checks crc 11. if crc from the atmel at88sa100s is incorrect, indication transmission error, system res ends transmit flag 12. system sends sleep flag to the atmel at88sa100s all commands other than m ac have a short execution delay. i n these cases the system should omit steps six , seven and eight and replace this with a wait of duration t parse + t exec . 4.4. synchronization because the communications protocol is half duplex, there is the possibility that the system and the at88sa100s will fall out of synchronization with each other. in order to speed recovery, the at88sa100s implements a timeout that forces the at88sa100s to sleep. see section 4.4.1 .
12 atmel a t88sa10 0 s 8558e ? smem ? 8/10 4.4.1. io timeout after a leading tran sition for any data token has been received, the atmel ? at88sa100s will expect the remaining bits of the token to be properly received by the chip within the t timeout interval. failure to send enough bits or the transmission of an illegal token (a low puls e exceeding t zlo ) will cause the chip to enter the sleep state after the t timeout interval. the same timeout applies during the transmission of the command block. after the transmission of a legal command flag, the io timeout circuitry is enabled until th e last expected data bit is received. note: t he timeout counter is reset after every legal token, so the total time to transmit the command may exceed the t timeout interval whil e the time between bits may not in order to limit the active current if the at88sa1 00s is inadverten t ly awakened, the io t imeout circuitry is also enabled when the at88sa100s receives a wake - up. if the first token does not come within the t timeout interval, then the at88sa100s will go back to the sleep mode without performing any operati ons. the io timeout circuitry is disabled when the chip is busy executing a command. 4.4.2. synchronization procedures when the system and the at88sa100s fall out of synchronization, the system will ultimately end up sending a t ransmit flag which will not generat e a response from the at88sa100s . the system should implement its own timeout which waits for t timeout during which time the at88sa100s should go to sleep automatically. at this point, the system should send a wake token and after t wlo + t whi , a transmit t oken. the 0x11 status indicates that the resynchronization was successful. it may be possible that the system does not get the 0x11 code from the at88sa100s for one of the following reasons: 1. the system did not wait a full t timeout delay with the io signal idle in which case the atmel at88sa100s may have interpreted the w ake token and t ransmit flag as a data bits. recommended resolution is to wait twice the t timeout de lay and re - issue the wake token. 2. the atmel at88sa100s went into the sleep mode for some rea son while the system was transmitting data. in this case, the atmel at88sa100s will interpret the next data bit as a w ake token, but ignore some of the subsequently transmitted bits during its wake - up delay. if any bytes are transmitted after the wake - up d elay, they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct crc. recommended resolution is to wait the t timeout de lay and re- issue the wake token. 3. there is some internal error condition within the atmel at88sa100s which will b e automatically reset after a t watchdog interval, see below. there is no way to externally reset the atmel at88sa100s ? the system should leave the io pin idle for this in terval and issue the wake token. 4.5. watchdog failsafe after the w ake token has been received by the at88sa100s , a watchdog counter is s tarted within the chip. after t watchdog , the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some io transmission is in progress. there is no way to reset the counter other than to put the chip to sleep and wake it up again. this is implemented as a fail - safe so that no matter what happens on either the system side or ins ide the various state machines of the at88sa100s including any io synchronization issue, power consumption will fall to the low sleep level automatically.
atmel at88sa10 0 s 13 8558e ? smem ? 8/10 4.6. byte and bit ordering the atmel ? at88sa100s is a little - endian chip: ? all multi - byte aggregate elemen ts within this spec are treated as arrays of bytes and are processed in the order received ? data is transferred to/from the atmel at88sa100s least significant bit first on the bus ? in this document, the most significant bit appears towards the left hand side of the page 5. commands th e command packet is broken down in the following way: byte name meaning 0 opcode the command code 1 param1 the first parameter ? always present 2 -3 param2 the second parameter ? always present 4 + data optional remaining input d ata if a command fails because the crc within the block is incorrect, the opcode is invalid or one of the parameters is illegal, then immediately after t parse the system will be able to retrieve an error response block containing a single byte packet. th e value of that byte will be either 0x0f or 0xff depending on the source of the error. see section 4.1.2 . if a command is received successfully then after the appropriate execution delay the system will be able to retrieve the output block as described in the individual command descriptions below. in the individual command description tables below, the size column describes the number of bytes in the parameter documented in each particular row . the total size of the block for each of the commands is fixed, though that value is different for each command. if the block size for a particular command is incorrect, the chip will not attempt the command execution and return an error.
14 atmel a t88sa10 0 s 8558e ? smem ? 8/10 5.1. mac computes a sha - 256 digest of the key , challenge and other fixed information on the chip to generate an output response. if memvalid is not set, indicating that no valid key is stored in the sram, then this command will return an error. the hashed message includes the following bytes, concate nated in this order: 256- bits key (stored in sram) 256- bits challenge 8 - bits opcode (always 0x0 8 ) 8 - bits mode input 16- bits param2 input 88- bits all zeros 8 - bits fuse mfrid ( fuse[88- 95] ) 32- bits fuse sn ( fuse[96 - 127] ) or zeros 16- bits rom mfrid 16- bits rom sn or zeros 1 - bit 1?s ? sha - 256 padding 255- bits 0?s ? sha - 256 padding 64- bits length (704) per sha -256 table 5 -1. input parameters name size notes opcode mac 1 0x0 8 param1 mode 1 refer to tabl e 5- 3 param2 zero 2 must be 0x00 00 data challenge 32 input portion of m essage to be digested table 5 -2. output parameters name size notes response 32 sha - 256 digest table 5 -3. mode encoding bit notes 6 if set, then the four bytes of fuse sn and the two bytes of rom sn w ill be included in the message, otherwise these bits will be set to zero in the message 0 - 5, 7 ignored, must be all zero
atmel at88sa10 0 s 15 8558e ? smem ? 8/10 5.2. read reads four bytes from fuse , rom or memvalid. any attempt to present the chip with an illegal fuse address will result in an e rror return. table 5 -4. input parameters name size notes opcode read 1 0x02 param1 mode 1 fuse , rom or memvalid . see to table 12 param2 address 2 which 4 - bytes within array . bits 2 - 15 are ignored by the chip and should be zeros data ? 0 table 5 -5. output parameters name size notes contents 4 the contents of the specified memory location table 5 -6. mode encoding name value notes rom 0x00 reads four bytes from the rom. bit 1 of the address parameter must be zero fuse 0x01 reads the value of 32 - fuses memvalid 0x03 returns four byt es. the lsb of the first byte indicates whether or not the contents of the sram are valid. all other bits in all bytes have a value of zero . the address parameter is ignored 5.3. burnfuse burns one of the 88 user accessible fuse bits. the values in fuses # 8 8 - 127 are reserved for fuse mfr id and fuse sn and cannot be blown via this command. all addresses above 0x 57 (87) will result in an error. fuses, with the exception of those initialized by atmel ? , have a value of one on shipment from the atmel factory and t ransition to a zero when they are b urned . fuse bits zero through seven of the fuse array are word lock bits. b urning one of these has the effect of locking the corresponding 16 - bit word within fuse . bit zero locks fuses 0 - 15, bit one locks fuses 16 - 31 and so on. if bit zero is burned, then the value of the lock bits can no longer be changed. the values of lock bits six and seven are ignored by the chip. the power supply pin must meet the v burn specificat ion during the entire burnfuse command in order to bur n fuses reliably. if vcc is greater than 4.5v, then the burntime parameter should be set to 0x00 and the internal burn time will be 250 s. if vcc is less than 4.5v but greater than v burn then the burntim e parameter should be set to 0x8 000 and the internal burn time will be up to 1 9 0 ms. the chip does not internally check the supply voltage level. there is a very small interval during t exec_burn when the fuse element is actually being burned. the power supply must not be removed during this interval and the watchdog timer must not be allowed to expire during this interval, or the fuse may end up in a state where it reads as un - burned but cannot be burned.
16 atmel a t88sa10 0 s 8558e ? smem ? 8/10 table 5 -7. input parameters name size notes opcode burnfuse 1 0x04 param1 fusenum 1 which bit within fuse array, mini mum value is 0, and maximum value is 87 param2 burntime 2 must be 0x00 00 if vcc > 4.5v, must be 0x8 0 00 otherwise data ? 0 table 5 -8. output parameters name size notes success 1 upon successful completion, a value of 0 will be returned by the atmel at88sa1 00s 5.4. genpersonalizationkey this command generates a decryption digest that will be used by the subsequent command (loadsram) to decrypt the key value that is to be written into the sram. this command must be run immediately prior to loadsram within the sam e watchdog cycle. this command l oads a transport key from an internal secure storage location and then uses that key along with an input seed to generate a decryption digest using sha - 256. neither the transport key nor the decryption digest can be read fro m the chip. upon completion, an internal bit is set indicating that the decryption digest has been generated and is ready to use by loadsram. this bit is cleared (and the digest lost) when the watchdog timer expires , the chip goes to sleep or the power is cycled. table 5 -9. input parameters name size notes opcode genpers 1 0x2 0 param1 zero 1 must be 0x00 param2 keyid 2 identification number of the personalization key to be loaded data seed 16 seed for digest generation. the least significant bit of the last byte is ignored. table 5 - 10. output parameter name size notes success 1 upon successful execution, a value of 0 will be returned by the atmel at88 sa100s chip the sha - 256 message body used to create the decryption digest which is internally stored in the chi p consists o f the following 512 - bits: 256- bits stored key[keyid] 64- bits all 1?s 127- bits input seed 1 - bit ?1? pad 64- bits length of message in bits, fixed at 447
atmel at88sa10 0 s 17 8558e ? smem ? 8/10 5.5. loadsram writes 256 - bits into the battery backed sram and locks th is memory against further mod ification. the value in the battery backed sram cannot be read, it must be verified via the mac command. if the secret value in the sram is already valid then this command will fail with an error response. the only way to unlock the sram is to remove power from the atmel ? at88sa100s . the input data (secret key) is always decrypted using the decryption digest previously generated by genpersonalizationkey prior to being written into the battery backed sram. note: b oth the genpersonalizationkey and loadsram commands must be run consecutively within a single w ake cycle prior to the expiration of the watchdog timer. if any command is inserted between these two operations then loadsram will fail. table 5 - 11. input parameters name size notes opcode loadsram 1 0x1 0 param1 zero1 1 must be 0x00 param2 zero2 2 must be 0x00 00 data key 32 encrypted value to be written into the sram table 5 - 12. output parameter name size notes success 1 upon successful execution, a value of 0 will be returned by the atmel at88 sa100s chip the at88 sa100s chip executes the following sequence on receipt of this command. 1. if the internal flag (indicating that a personalization key has been loaded) is not set, then return error. if the memvalid f lag is set, return error 2. successively xor each byte in the data (secre t key) parameter with the corresponding byte from the personalization key gen erated by genpersonalizationkey 3. transfer the resulting b ytes to the battery backed sram 4. set memvalid (internal flag) to one 5.6. pauselong forces the chip into the pause state until th e watchdog timer expires, after which it will automatically enter into the sleep state. during execution of this command the chip will ignore all activity on the io signal. this command is used to prevent bus conflicts in a system that also includes the at mel cryptoauthentication ? host chip sharing the same signal wire. table 5 - 13. input parameters name size notes opode pauselong 1 0x0 1 param1 selector 1 which chip to put i nt o the pause state , 0x00 for all chips param2 zero 2 must be 0x00 00 data ignored 0
18 atmel a t88sa10 0 s 8558e ? smem ? 8/10 table 5 - 14. outp ut parameter name size notes success 1 if the command indicates that some other chip should go in to the pause state , a value of zero will be returned by th is atmel at88 sa100s chip . if this chip goes into the pause state no value will be returned . the se lector parameter provides a mechanism to select which atmel at88sa100s will pause if there are multiple devices on the bus: ? if the selector parameter is 0x00, then every chip receiving this command will go in to the pause state and no chip will return a suc cess code . ? if any of the bits of the selector parameter are set , then the chip will read the values of fuse[ 84- 8 7] and go to sleep only if those fuse values match the least significant four bits of the selector parameter. if the chip does not go in to the p ause state , it returns a n error code of 0x0f. o therwise it goes in to the pause state and never returns any code . 6. pinout table 6 -1. sot pin definitions pin # name description 1 signal io channel to the system, open drain output. it is expected that an external pull - up resistor will be provided to pull this signal up to v cc for proper communications. when the chip is not in use this pin can be pulled to either v cc or v ss 2 v cc power supply, 2. 7 ? 5. 2 5v. this pin should be bypassed with a high quality 0.1 f capacitor close to this pin with a short trace to v ss additional applications information at www.atmel.com 3 v ss connect to system ground table 6 -2. tssop and soic pin definitions pin # name description 4 v ss connect to system ground 5 signal io channel to the system, open drain output. it is expected that an external pull - up resistor will be provided to pull this signal up to v cc for proper communications. when the chip is not in use this pin can be pulled to either v cc or v ss 8 v cc p ower supply, 2. 7 ? 5. 2 5v. this pin should be bypassed with a high quality 0.1 f capacitor close to this pin with a short trace to v ss additional applications information at www.atmel.com
atmel at88sa10 0 s 19 8558e ? smem ? 8/10 7. package drawing s 3ts1 ? shr ink sot p a c k a g e d r a w i n g c o n t a c t : p a c k a g e d r a w i n g s @ a t m e l . c o m t i t l e d r a w i n g n o . g p c r r e v . 3 t s 1 1 2 / 1 1 / 0 9 c o m m o n d i m e n s i o n s ( u n i t o f m e a s u r e = m m ) s y m b o l m i n n o m m a x n o t e e n d v i e w s i d e v i e w t o p v i e w 3 t s 1 , 3 - l e a d , 1 . 3 0 m m b o d y , p l a s t i c t h i n s h r i n k s m a l l o u t l i n e p a c k a g e ( s h r i n k s o t ) b t b g 0.89 0.01 0.88 2.80 2.10 1.20 0.30 a a1 a2 d e e1 l1 e1 b - - - 2.90 - 1.30 0.54 ref 1.90 bsc - 1.12 0.10 1.02 3.04 2.64 1.40 0.50 1,2 1,2 3 notes: 1. dimension d does not include mold flash, protrusion s or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.25mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusi on shall not exceed 0.25mm per side. 2. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. these dimensions apply to the flat section of the lead between 0.08 mm and 0.15mm from the lead tip. this drawing is for general information only. refer to jed ec drawing to-236, variation ab for additional information. c l l1 3 e e1 1 2 e1 seating plane b a2 a a1 e d gnd sd a v cc
20 atmel a t88sa10 0 s 8558e ? smem ? 8/10 8 a2 ? tssop p a c k a g e d r a w i n g c o n t a c t : p a c k a g e d r a w i n g s @ a t m e l . c o m d r a w i n g n o . r e v . t i t l e g p c common dimensi ons (unit of measure = mm) symbol min nom max no te d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref s i d e v i ew end vie w t op vie w a2 a l l1 d 1 2 3 e1 n b pin 1 indica tor this cor ner e e notes: 1. this dr a wing is f or gener al inf or mation only . ref er to jedec dr a wing mo-153, v ar iation aa, f or proper dimensions , toler ances , datums , etc. 2. dimension d does not include mold flash, protr usions or gate b urrs . mold flash, protr usions and gate b urrs shall not e xceed 0.15mm (0.006in) per side . 3. dimension e1 does not include inter-lead flash or protr usions . inter-lead flash and protr usions shall not e xceed 0.25mm (0.010in) per side . 4. dimension b does not inc lude dambar protr usion. allo w ab le dambar protr usion shall be 0.08mm total in e xcess of the b dimension at maxim um mater ial condition. dambar cannot be located on the lo w er r adius of the f oot. minim um space betw een protr usion and adjacent lead is 0.07mm. 5. dimension d and e1 to be deter mined at datum plane h. 8 a 2 e 5 / 1 9 / 1 0 8a2, 8-lead 4.4mm bod y , plastic thin shr ink small outline p ac kage (tssop) tnr
atmel at88sa10 0 s 21 8558e ? smem ? 8/10 8s1 ? jedec soic p a c k a g e d r a w i n g c o n t a c t : p a c k a g e d r a w i n g s @ a t m e l . c o m d r a w i n g n o . r e v . t i t l e g p c common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? 8 e n d v i e w 8 s 1 f 5 / 1 9 / 1 0 notes: this dr a wing is f or gener al inf or mation only . ref er to jedec dr a wing ms-012, v ar iation aa f or proper dimensions , toler ances , datums , etc. 8s1, 8-lead (0.150? wide bod y), plastic gull wing small outline (jedec soic) swb
22 atmel a t88sa10 0 s 8558e ? smem ? 8/10 8. ordering information ordering code package type temperature range at 88s a 100s -sh -cz -t soic, tape & reel - 40 c to 85 c at 88s a 100s -t h -cz -t tssop, tape & reel - 40 c to 85 c at 88s a 100s - tsu -t 3ld sot23 , tape & reel - 40 c to 85 c 9. revision history doc. rev. date comments 8558e 0 8 /20 1 0 update io timeout description 8558d 0 6 /20 1 0 update to table 3: ac parameters 8558c 0 5 /20 1 0 expansion of io timeout specification 8558b 0 4 /20 1 0 add tssop and soic packages 8558a 0 3 /2009 initial document release
8558e ? smem ? 8/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1) (408) 441 - 0311 fax: (+1) (408) 487 - 2600 www.atmel.com atmel asia limited unit 01 - 5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245 - 6100 fax: (+852) 2722 - 1369 atmel munich gmbh business campus parkring 4 d - 85748 garching b. munich germany tel: (+49) 89 - 31970- 0 fax: (+49) 89 - 3194621 atmel japan 9f, ton etsu shinkawa bldg. 1 - 24- 8 shinkawa chuo - ku, tokyo 104 - 0033 japan tel: (+81) (3) 3523 - 3551 fax: (+81) (3) 3523 - 7581 product contact technical support securemem@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no licen se, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and conditions of sale located on atmel?s web site, atme l assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular pur pose, or non - infringement. in no event s hall atmel be liable for any direct, indirect, consequential, punitive, special or inciden - tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising o ut of the use or inability to use th is document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificati ons and product descriptions at any time without notice. atmel does not make any commitment to update the information contained herei n. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applic ations. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 20 10 atmel corporation . all rights reserved. atmel ? , atmel l ogo and combinations thereof, and others are regis tered trademarks , cryptoauthentication? and others, a r e trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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